1. Field of the Invention
The present invention relates to a memory device having at least one repeater for address signals and control signals, and more particularly to a memory device having at least one repeater for preventing signal delay created when lengths of address signal lines and control signal lines become long.
2. Description of the Prior Art
In general, address signals and control signals applied to address pads and control pads are inputted into memory core blocks (banks) through address drivers and control drivers, respectively.
However, as the size of a semiconductor device becomes enlarged, it is necessary for the address signals and control signals to be transmitted faraway. Herein, the control signals includes row address control signals, column address control signals, and bank control signals used in a memory device. The address signals includes row addresses and column addresses.
FIG. 1 is a view for explaining the routing of address signals and control signals according to the prior art.
As shown in FIG. 1, address signals and control signals are outputted from drivers adjacent to pads so as to be transmitted into memory core blocks (i.e., banks). As the size of the semiconductor chip becomes larger, the signals must be transmitted farther. Such a long transmission length increases resistance component and capacitance component of signal lines, thereby delaying the time for a signal transmission. Also, a long signal line may distort a signal due to a crosstalk with adjacent signals. Such distortion of the signal may cause an unexpected timing delay. The unexpected timing delay may reduce a timing margin with respect to other control signals, thereby resulting fail of chips.
Also, if an exact timing control for a near-side bank and a far-side bank is not performed, the timing of a data signal outputted from a bank by means of a control signal is not exactly controlled. Therefore, a bank remote from a data pad outputs data too late, and a bank adjacent to the data pad outputs data too early. In this case, since the timing control for data output is not smoothly performed, erroneous data can be outputted through the data pad.